A Low Latency Standard Basis Gf(2m) Multiplier

A new parallel-in-parallel-out bit-level pipelined multi-plier is presented to perform multiplication in GF(2 m). The existing designs use m 2 identical cells each having 7 latches and have a system latency of 3m. We start with the Dependence Graph (DG) of the algorithm and pipleine it to achieve a critical path equal to the delay of a 2-input AND and XOR gate. The critical path in the proposed design is the same as in previous designs. The number of latches required per cell has however, been reduced from 7 to 3. This results in considerable hardware savings and the system latency is also reduced form the present 3m to m+1 in the proposed design. A chip has been designed using Magic to implement the proposed multiplier.